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16-Port, 36V Constant-Current LED Driver
Detailed Description
The MAX6971 LED driver comprises a 4-wire serial
interface driving 16 constant-current-sinking, open-
drain output ports. The outputs drive LEDs in either
static or multiplex applications (Figure 1). The constant-
current outputs are guaranteed for current accuracy
not only with chip-supply voltage variations (5V ±10%
and 3V to 5.5V), but also over a realistic range of driver
output voltage drop (0.8V to 2.5V). The drivers use cur-
rent-sensing feedback circuitry (not simple current mir-
rors) to ensure very small current variations over the full
allowed range of output voltage (see the Typical
Operating Characteristics ).
The 4-wire serial interface comprises a 16-bit shift reg-
ister and a 16-bit transparent latch. The shift register is
written through a clock input, CLK, and a data input,
DIN, and the data propagates to a data output, DOUT.
The data output allows multiple drivers to be cascaded
and operated together. The contents of the 16-bit shift
register are loaded into the transparent latch through a
latch-enable input, LE. The latch is transparent to the
shift register outputs when high, and latches the current
state on the falling edge of LE.
Each driver output is an open-drain, constant-current
sink that should be connected to the cathode of either
a single LED or a series string of multiple LEDs. The
LED anode can be connected to a supply voltage of up
to 36V, independent of the MAX6971 supply, V+. The
constant-current capability is up to 55mA per output,
set for all eight outputs by an external resistor, R SET .
4-Wire Serial Interface
The serial interface on the MAX6971 is a 4-wire serial
interface using four inputs (DIN, CLK, LE, OE ) and a
data output (DOUT). This interface is used to write dis-
play data to the MAX6971. The serial-interface data
word length is 16 bits, D0–D15. See Figure 2.
The functions of the five interface pins are as follows.
DIN is the serial-data input, and must be stable when it
is sampled on the rising edge of CLK. Data is shifted in,
MSB first. This means that data bit D15 is clocked in
first, followed by 15 more data bits finishing with the
LSB, D0.
LE
t CL
t CH
t CP
t LS
t LW
t LF
CLK
t DH
t DS
DIN
D15
D14
D1
D0
t DO
DOUT
OE
t OEL
t OEW
t OEH
D7
80%
.
OUT_
Figure 2. 4-Wire Serial-Interface Timing Diagram
t f
20%
t r
_______________________________________________________________________________________
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